Sciweavers

ISMVL
2000
IEEE
111views Hardware» more  ISMVL 2000»
14 years 1 months ago
De Morgan Bisemilattices
Janusz A. Brzozowski
ISMVL
2000
IEEE
134views Hardware» more  ISMVL 2000»
14 years 1 months ago
The 2-SAT Problem of Regular Signed CNF Formulas
Signed conjunctive normal form (signed CNF) is a classical conjunctive clause form using a generalized notion of literal, called signed atom. A signed atom is an expression of the...
Bernhard Beckert, Reiner Hähnle, Felip Many&a...
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 1 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 1 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ISCA
2000
IEEE
97views Hardware» more  ISCA 2000»
14 years 1 months ago
Energy-driven integrated hardware-software optimizations using SimplePower
Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary ...
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
14 years 1 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
14 years 1 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
14 years 1 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ISCA
2000
IEEE
94views Hardware» more  ISCA 2000»
14 years 1 months ago
A hardware mechanism for dynamic extraction and relayout of program hot spots
Matthew C. Merten, Andrew R. Trick, Erik M. Nystro...
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
14 years 1 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens