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MICRO
2000
IEEE
68views Hardware» more  MICRO 2000»
14 years 1 months ago
Efficient checker processor design
The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implemen...
Saugata Chatterjee, Christopher T. Weaver, Todd M....
MICRO
2000
IEEE
96views Hardware» more  MICRO 2000»
14 years 1 months ago
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and c...
Amirali Baniasadi, Andreas Moshovos
MICRO
2000
IEEE
81views Hardware» more  MICRO 2000»
14 years 1 months ago
A static power model for architects
J. Adam Butts, Gurindar S. Sohi
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
14 years 1 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
ITC
2000
IEEE
108views Hardware» more  ITC 2000»
14 years 1 months ago
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
Zoran Stanojevic, Hari Balachandran, D. M. H. Walk...
ITC
2000
IEEE
88views Hardware» more  ITC 2000»
14 years 1 months ago
Predicting device performance from pass/fail transient signal analysis data
Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, a technique based o...
James F. Plusquellic, Amy Germida, Jonathan Hudson...
ITC
2000
IEEE
76views Hardware» more  ITC 2000»
14 years 1 months ago
System issues in boundary-scan board test
Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of p...
Kenneth P. Parker
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
14 years 1 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey