DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a novel method for developing reconfigurable systems targeted at embedded system applications. We show how an existing object oriented design method (MOOSE) has been ad...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper, we present an efficient yet accurate inductance extraction methodology and also apply it to clocktree RLC extraction. We first show that without loss of accuracy, t...