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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 1 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DATE
2000
IEEE
78views Hardware» more  DATE 2000»
14 years 1 months ago
HW/SW Codesign of an Engine Management System
The design process for an engine management system is presented. The functional specification of the system has been captured using C and C++ as specification languages. The val...
Massimo Baleani, Alberto Ferrari, Alberto L. Sangi...
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
14 years 1 months ago
Automatic Abstraction for Worst-Case Analysis of Discrete Systems
c Abstraction for Worst-Case Analysis of Discrete Systems Felice Balarin Cadence Berkeley Laboratories Recently, a methodology for worst-case analysis of discrete systems has been...
Felice Balarin
DATE
2000
IEEE
112views Hardware» more  DATE 2000»
14 years 1 months ago
A Discrete-Time Battery Model for High-Level Power Estimation
In this paper, we introduce a discrete-time model for the complete power supply sub-system that closely approximates the behavior of its circuit-level (i.e., HSpice), continuous-t...
Luca Benini, Giuliano Castelli, Alberto Macii, Enr...
ATS
2000
IEEE
98views Hardware» more  ATS 2000»
14 years 1 months ago
Embedded core testing using genetic algorithms
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
Ruofan Xu, Michael S. Hsiao
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
14 years 1 months ago
Efficient built-in self-test algorithm for memory
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
Sying-Jyan Wang, Chen-Jung Wei
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
14 years 1 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
ATS
2000
IEEE
57views Hardware» more  ATS 2000»
14 years 1 months ago
Fast hierarchical test path construction for DFT-free controller-datapath circuits
Yiorgos Makris, Jamison Collins, Alex Orailoglu
ATS
2000
IEEE
116views Hardware» more  ATS 2000»
14 years 1 months ago
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
Said Hamdioui, A. J. van de Goor