ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
An algorithmic fault detection scheme for linear digital state variable systems is proposed. The proposed scheme eliminates the necessity of observing the internal states of the s...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
ASYNC
2000
IEEE
14 years 1 months ago
2000
IEEE
ASYNC
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper we describe a complete design methodology for a globally asynchronous onchip communication network connecting both locally-synchronous and asynchronous modules. Sync...
ASYNC
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper brings together a selection of creative circuit designs and ideas that Charles Molnar devised while working at Sun Microsystems Laboratories. The circuits offer fast im...
ASYNC
2000
IEEE
14 years 1 months ago
2000
IEEE
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...