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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
14 years 1 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
DATE
2000
IEEE
129views Hardware» more  DATE 2000»
14 years 1 months ago
Non-Linear Components for Mixed Circuits Analog Front-End
This paper presents the development of some frontend analog circuits for mixed signals systems. The paper proposes the use of externally linear, internally nonlinear analog circui...
Luigi Carro, Adão Antônio de Souza Jr...
DATE
2000
IEEE
105views Hardware» more  DATE 2000»
14 years 1 months ago
System Synthesis for Multiprocessor Embedded Applications
This paper presents the system synthesis techniques available in S3 E2 S, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that ca...
Luigi Carro, Márcio Eduardo Kreutz, Fl&aacu...
DATE
2000
IEEE
69views Hardware» more  DATE 2000»
14 years 1 months ago
Detecting Undetectable Controller Faults Using Power Analysis
Joan Carletta, Christos A. Papachristou, Mehrdad N...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
14 years 1 months ago
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow
We integrate data and control flow at the system specification level, using the two specialized and well established languages Matlab and SDL. For this we provide a modeling techn...
Per Bjuréus, Axel Jantsch
DATE
2000
IEEE
139views Hardware» more  DATE 2000»
14 years 1 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
DATE
2000
IEEE
75views Hardware» more  DATE 2000»
14 years 1 months ago
Layout Compaction for Yield Optimization via Critical Area Minimization
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
Youcef Bourai, C.-J. Richard Shi
DATE
2000
IEEE
99views Hardware» more  DATE 2000»
14 years 1 months ago
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki