Sciweavers

ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
14 years 1 months ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
ASYNC
2000
IEEE
181views Hardware» more  ASYNC 2000»
14 years 1 months ago
Asynchronous Design Using Commercial HDL Synthesis Tools
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
Michiel M. Ligthart, Karl Fant, Ross Smith, Alexan...
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
14 years 1 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
ASYNC
2000
IEEE
138views Hardware» more  ASYNC 2000»
14 years 1 months ago
Low-Latency Asynchronous FIFO's Using Token Rings
This paper presents several new asynchronous FIFO designs. While most existing FIFO’s trade higher throughput for higher latency, our goal is to achieve very low latency while m...
Tiberiu Chelcea, Steven M. Nowick
ASYNC
2000
IEEE
95views Hardware» more  ASYNC 2000»
14 years 1 months ago
Composing Snippets
The following pages contain the final version for a chapter in the book Advances in Concurrency and Hardware Design (ACHD), to be published by Springer-Verlag in 2002. The editor...
Igor Benko, Jo C. Ebergen
ASYNC
2000
IEEE
107views Hardware» more  ASYNC 2000»
14 years 1 months ago
AMULET3i - An Asynchronous System-on-Chip
AMULET3i is the third generation asynchronous ARMcompatible microprocessor subsystem developed at the University of Manchester. It is internally modular, being based around the MA...
Jim D. Garside, W. J. Bainbridge, Andrew Bardsley,...
ASAP
2000
IEEE
141views Hardware» more  ASAP 2000»
14 years 1 months ago
Bit Permutation Instructions for Accelerating Software Cryptography
Permutation is widely used in cryptographic algorithms. However, it is not well-supported in existing instruction sets. In this paper, two instructions, PPERM3R and GRP, are propo...
Zhijie Shi, Ruby B. Lee
ASAP
2000
IEEE
96views Hardware» more  ASAP 2000»
14 years 1 months ago
High-Level Synthesis of Nonprogrammable Hardware Accelerators
Robert Schreiber, Shail Aditya, B. Ramakrishna Rau...
ASAP
2000
IEEE
110views Hardware» more  ASAP 2000»
14 years 1 months ago
Compiling Image Processing Applications to Reconfigurable Hardware
Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A....