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MICRO
2002
IEEE
127views Hardware» more  MICRO 2002»
14 years 1 months ago
DELI: a new run-time control point
The Dynamic Execution Layer Interface (DELI) offers the following unique capability: it provides fine-grain control over the execution of programs, by allowing its clients to obse...
Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwal...
MICRO
2002
IEEE
105views Hardware» more  MICRO 2002»
14 years 1 months ago
Power protocol: reducing power dissipation on off-chip data buses
K. Basu, Alok N. Choudhary, Jayaprakash Pisharath,...
MICRO
2002
IEEE
113views Hardware» more  MICRO 2002»
14 years 1 months ago
Vacuum packing: extracting hardware-detected program phases for post-link optimization
This paper presents Vacuum Packing, a new approach to profile-based program optimization. Instead of using traditional aggregate or summarized execution profile weights, this ap...
Ronald D. Barnes, Erik M. Nystrom, Matthew C. Mert...
MICRO
2002
IEEE
118views Hardware» more  MICRO 2002»
14 years 1 months ago
Exploiting data-width locality to increase superscalar execution bandwidth
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
Gabriel H. Loh
MICRO
2002
IEEE
114views Hardware» more  MICRO 2002»
14 years 1 months ago
Characterizing and predicting value degree of use
A value’s degree of use—the number of dynamic uses of that value—provides the most essential information needed to optimize its communication. We present simulation results ...
J. Adam Butts, Gurindar S. Sohi
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
14 years 1 months ago
Pointer cache assisted prefetching
Data prefetching effectively reduces the negative effects of long load latencies on the performance of modern processors. Hardware prefetchers employ hardware structures to predic...
Jamison D. Collins, Suleyman Sair, Brad Calder, De...
ITC
2002
IEEE
83views Hardware» more  ITC 2002»
14 years 1 months ago
Packet-Based Input Test Data Compression Techniques
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 1 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
ITC
2002
IEEE
102views Hardware» more  ITC 2002»
14 years 1 months ago
Fault Grading FPGA Interconnect Test Configurations
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin T...
ITC
2002
IEEE
99views Hardware» more  ITC 2002»
14 years 1 months ago
An Embedded Core for Sub-Picosecond Timing Measurements
The continued market demand for GHz processors and high-capacity communication systems results in an increasing number of low-cost high volume ICs with multi-GHz clocks and/or mul...
Sassan Tabatabaei, André Ivanov