ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fa...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
— Multiple power supply voltages are often used in modern high performance ICs such as microprocessors to decrease power consumption without affecting circuit speed. The system o...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is ...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...