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DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 2 months ago
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits
This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this ...
Carlos Eduardo Savioli, Claudio C. Czendrodi, Jos&...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 2 months ago
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
Raja K. K. R. Sandireddy, Vishwani D. Agrawal
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperat...
José Luis Rosselló, Vicens Canals, S...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 2 months ago
Rapid Generation of Thermal-Safe Test Schedules
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
DATE
2005
IEEE
93views Hardware» more  DATE 2005»
14 years 2 months ago
Model Reuse through Hardware Design Patterns
Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices h...
Fernando Rincón, Francisco Moya, Jesú...
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 2 months ago
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
Elvinia Riccobene, Patrizia Scandurra, Alberto Ros...