This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this ...
Carlos Eduardo Savioli, Claudio C. Czendrodi, Jos&...
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperat...
Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently ...
Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu...
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices h...
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
Elvinia Riccobene, Patrizia Scandurra, Alberto Ros...