DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
With growing computational needs of many real-world applications, frequently changing specifications of standards, and the high design and NRE costs of ASICs, an algorithm-agile ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space r...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Main memories can consume a large percentage of overall energy in many data-intensive embedded applications. The past research proposed and evaluated memory banking as a possible ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...