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DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
An Efficient Sequential SAT Solver With Improved Search Strategies
Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, L...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
A New Embedded Measurement Structure for eDRAM Capacitor
Laurent Lopez, Jean Michel Portal, Didier Né...
DATE
2005
IEEE
101views Hardware» more  DATE 2005»
14 years 2 months ago
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at e...
Celia López-Ongil, Mario García-Vald...
DATE
2005
IEEE
84views Hardware» more  DATE 2005»
14 years 2 months ago
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Mirko Loghi, Paolo Azzoni, Massimo Poncino
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
14 years 2 months ago
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...
Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
14 years 2 months ago
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parame...
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, S...
DATE
2005
IEEE
129views Hardware» more  DATE 2005»
14 years 2 months ago
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construc...
Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 2 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...