DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid’s...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...