Sciweavers

DATE
2005
IEEE
102views Hardware» more  DATE 2005»
14 years 2 months ago
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach
Rabeb Kheriji, V. Danelon, Jean-Louis Carbon&eacut...
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
14 years 2 months ago
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
Jawad Khan, Ranga Vemuri
DATE
2005
IEEE
224views Hardware» more  DATE 2005»
14 years 2 months ago
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially ...
David C. Keezer, C. Gray, A. M. Majid, N. Taher
DATE
2005
IEEE
129views Hardware» more  DATE 2005»
14 years 2 months ago
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications
In this paper, the program control unit of an embedded RISC processor is enhanced with a novel zerooverhead loop controller (ZOLC) supporting arbitrary loop structures with multip...
Nikolaos Kavvadias, Spiridon Nikolaidis
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 2 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
DATE
2005
IEEE
98views Hardware» more  DATE 2005»
14 years 2 months ago
Space-Efficient Bounded Model Checking
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
14 years 2 months ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
DATE
2005
IEEE
82views Hardware» more  DATE 2005»
14 years 2 months ago
Energy-Aware Routing for E-Textile Applications
As the scale of electronic devices shrinks, “electronic textiles” (e-textiles) will make possible a wide variety of novel applications which are currently unfeasible. Due to t...
Jung-Chun Kao, Radu Marculescu
DATE
2005
IEEE
132views Hardware» more  DATE 2005»
14 years 2 months ago
Statistical Timing Analysis using Levelized Covariance Propagation
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for...
Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 2 months ago
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangy...