Sciweavers

DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission
Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication. The parasitic inductance within IC packaging causes bounce o...
Brock J. LaMeres, Sunil P. Khatri
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 2 months ago
UML 2.0 Profile for Embedded System Design
Unified Modeling Language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-Profile - that introduces a set of st...
Petri Kukkala, Jouni Riihimäki, Marko Hä...
DATE
2005
IEEE
153views Hardware» more  DATE 2005»
14 years 2 months ago
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
Smita Krishnaswamy, George F. Viamontes, Igor L. M...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 2 months ago
Systematic Transaction Level Modeling of Embedded Systems with SystemC
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
Wolfgang Klingauf
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
14 years 2 months ago
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami,...
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
14 years 2 months ago
Cantilever-Based Biosensors in CMOS Technology
Kay-Uwe Kirstein, Yue Li, Martin Zimmermann, Cyril...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 2 months ago
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resour...
Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jun...
DATE
2005
IEEE
176views Hardware» more  DATE 2005»
14 years 2 months ago
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
The new standard for digital video broadcast DVB-S2 features Low-Density Parity-Check (LDPC) codes as their channel coding scheme. The codes are defined for various code rates wi...
Frank Kienle, Torben Brack, Norbert Wehn