We propose a method for fine grain QoS control of dataflow applications. We assume that the application software is described as the composition of actions (C-functions) with qu...
Jacques Combaz, Jean-Claude Fernandez, Thierry Lep...
In this paper we introduce a new task model that is specifically targeted towards representing stream processing applications. Examples of such applications are those involved in...
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, ...
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
Most of the DNA chips available on the market are based on external or internal optical detection (fluorescence or chemiluminescence) and need a bulky chip reader (optics, laser, ...