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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 2 months ago
Fine Grain QoS Control for Multimedia Application Software
We propose a method for fine grain QoS control of dataflow applications. We assume that the application software is described as the composition of actions (C-functions) with qu...
Jacques Combaz, Jean-Claude Fernandez, Thierry Lep...
DATE
2005
IEEE
167views Hardware» more  DATE 2005»
14 years 2 months ago
A New Task Model for Streaming Applications and Its Schedulability Analysis
In this paper we introduce a new task model that is specifically targeted towards representing stream processing applications. Examples of such applications are those involved in...
Samarjit Chakraborty, Lothar Thiele
DATE
2005
IEEE
98views Hardware» more  DATE 2005»
14 years 2 months ago
Hardware Accelerated Power Estimation
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 2 months ago
C Compiler Retargeting Based on Instruction Semantics Models
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, ...
DATE
2005
IEEE
105views Hardware» more  DATE 2005»
14 years 2 months ago
A Novel Unified Architecture for Public-Key Cryptography
Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzoc...
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 2 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 2 months ago
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma...
DATE
2005
IEEE
160views Hardware» more  DATE 2005»
14 years 2 months ago
SOC Testing Methodology and Practice
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
Cheng-Wen Wu
DATE
2005
IEEE
152views Hardware» more  DATE 2005»
14 years 2 months ago
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
Fei Su, Krishnendu Chakrabarty
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 2 months ago
eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection
Most of the DNA chips available on the market are based on external or internal optical detection (fluorescence or chemiluminescence) and need a bulky chip reader (optics, laser, ...
Raymond Campagnolo