With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
This paper predicts self-heating effect in a short intrablock wire will arise as a design issue with technology scaling. The short intra-block wires are close to the substrate an...
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonock...
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
In this paper we address the problem of reducing the energy consumption in distributed embedded systems associated with time-constraints and equipped with fault-tolerant technique...
In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models pas...
Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGau...