DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes a novel algorithm that, given a data-flow graph and an input/output constraint, enumerates all convex subgraphs under the given constraint in polynomial time ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
Economic testing of small devices like LCD drivers is a real challenge. In this paper we describe an approach where a production tester is extended by a memory test engine (MTE). ...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
In highly power constrained sensor networks, harvesting energy from the environment makes prolonged or even perpetual execution feasible. In such energy harvesting systems, energy...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trust...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
— It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, a...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE