Sciweavers

DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 3 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 3 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
DATE
2007
IEEE
167views Hardware» more  DATE 2007»
14 years 3 months ago
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multip
We present a decomposition strategy to speed up constraint optimization for a representative multiprocessor scheduling problem. In the manner of Benders decomposition, our techniq...
Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
14 years 3 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
14 years 3 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 3 months ago
A non-intrusive isolation approach for soft cores
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
Ozgur Sinanoglu, Tsvetomir Petrov
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
14 years 3 months ago
What if you could design tomorrow's system today?
—This paper highlights a series of proven concepts aimed at facilitating the design of next generation systems. Practical system design examples are examined and provide insight ...
Neal Wingen
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 3 months ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
14 years 3 months ago
Reduction of detected acceptable faults for yield improvement via error-tolerance
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 3 months ago
Incremental ABV for functional validation of TL-to-RTL design refinement
Nicola Bombieri, Franco Fummi, Graziano Pravadelli