Moore’s Law will soon deliver tera-scale level transistor integration capacity. Power, variability, reliability, aging, and testing will pose as barriers and challenges to harne...
Shekhar Borkar, Norman P. Jouppi, Per Stenströ...
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, th...
Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or...
Abstract: An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical,...
Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-P...