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DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 3 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 3 months ago
Very wide register: an asymmetric register file organization for low power embedded processors
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 3 months ago
A two-tone test method for continuous-time adaptive equalizers
This paper describes a novel test method for continuous-time adaptive equalizers. This technique applies a two-sinusoidal-tone signal as stimulus and includes an RMS detector for ...
Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. P...
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
14 years 3 months ago
Computing synchronizer failure probabilities
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
Suwen Yang, Mark R. Greenstreet
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 3 months ago
Instruction-set customization for real-time embedded systems
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
Huynh Phung Huynh, Tulika Mitra
DATE
2007
IEEE
90views Hardware» more  DATE 2007»
14 years 3 months ago
Bus access optimisation for FlexRay-based distributed embedded systems
FlexRay will very likely become the de-facto standard for in-vehicle communications. Its main advantage is the combination of high speed static and dynamic transmission of message...
Traian Pop, Paul Pop, Petru Eles, Zebo Peng
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
14 years 3 months ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
DATE
2007
IEEE
74views Hardware» more  DATE 2007»
14 years 3 months ago
Modeling and simulation alternatives for the design of networked embedded systems
E. Alessio, Franco Fummi, Davide Quaglia, Maura Tu...
DATE
2007
IEEE
110views Hardware» more  DATE 2007»
14 years 3 months ago
Reconfigurable system-on-chip data processing units for space imaging instruments
Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. To overcome the limitations of trad...
Björn Fiethe, Harald Michalik, C. Dierker, Bj...