Sciweavers

DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 3 months ago
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Isabelle Puaut, Christophe Pais
DATE
2007
IEEE
139views Hardware» more  DATE 2007»
14 years 3 months ago
Efficient high-performance ASIC implementation of JPEG-LS encoder
- This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The prop...
Markos Papadonikolakis, Vasilleios Pantazis, Athan...
DATE
2007
IEEE
111views Hardware» more  DATE 2007»
14 years 3 months ago
CATS: cycle accurate transaction-driven simulation with multiple processor simulators
This paper focuses on enhancing performance of cycle accurate simulation with multiple processor simulators. Simulation performance is determined by how often simulators exchange ...
Dohyung Kim, Soonhoi Ha, Rajesh Gupta
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 3 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
DATE
2007
IEEE
96views Hardware» more  DATE 2007»
14 years 3 months ago
Self-heating-aware optimal wire sizing under Elmore delay model
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
Min Ni, Seda Ogrenci Memik
ASYNC
2007
IEEE
143views Hardware» more  ASYNC 2007»
14 years 3 months ago
Demystifying Data-Driven and Pausible Clocking Schemes
Robert D. Mullins, Simon W. Moore
ASYNC
2007
IEEE
103views Hardware» more  ASYNC 2007»
14 years 3 months ago
A Jitter Attenuating Timing Chain
Suwen Yang, Mark R. Greenstreet, Jihong Ren
ASYNC
2007
IEEE
107views Hardware» more  ASYNC 2007»
14 years 3 months ago
On-chip samplers for test and debug of asynchronous circuits
On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rel...
Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairba...