Sciweavers

ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
14 years 3 months ago
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase ...
Bin Zhang, Michael Orshansky
ISQED
2008
IEEE
98views Hardware» more  ISQED 2008»
14 years 3 months ago
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
We proposed a combined magnetic and circuit level technique to explore the design methodology of SpinTorque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling ju...
Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimit...
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
14 years 3 months ago
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
Rasit Onur Topaloglu
ISQED
2008
IEEE
66views Hardware» more  ISQED 2008»
14 years 3 months ago
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
Ming-Fang Lai, Hung-Ming Chen
ISQED
2008
IEEE
151views Hardware» more  ISQED 2008»
14 years 3 months ago
Quality of a Bit (QoB): A New Concept in Dependable SRAM
We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a typical mode, high-...
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 3 months ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty
ISQED
2008
IEEE
118views Hardware» more  ISQED 2008»
14 years 3 months ago
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
Enric Musoll
ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
14 years 3 months ago
Fundamental Data Retention Limits in SRAM Standby Experimental Results
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
ISQED
2008
IEEE
117views Hardware» more  ISQED 2008»
14 years 3 months ago
A Basis for Formal Robustness Checking
Correct input/output behavior of circuits in presence of internal malfunctions becomes more and more important. But reliable and efficient methods to measure this robustness are ...
Görschwin Fey, Rolf Drechsler