ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulati...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper examines latch style voltage mode sense amplifiers for operation in the sub-threshold region, where VDD<VT. We show that the offset gets worse relative to strong inv...