ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
Based Automatic Abstraction for CTL Model Checking Woohyuk Lee Abelardo Pardo Jae-Young Jang Gary Hachtel Fabio Somenzi University of Colorado ECEN Campus Box 425 Boulder, CO, 8030...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
Abstract - Using the
exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR p...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
This paper presents Metamorphosis1
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
A methodology for hierarchicalstatistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principalcompon...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...