In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a genera...
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area...
In a constraint-drivenlayout synthesisenvironment,parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specif...
Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, ...
A number of methods are presentedfor highly efficient calculation of substratecurrenttransport. A three-dimensionalGreen'sFunction based substrate representation, in combinat...
Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sang...
This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits dierent graph coloring and ...
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Although numerous methods have been proposed for interconnect simulation, no single model exists for all kind of transmission line problems. This paper presents a new, single, gen...