This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
We presenta new representationfor Boolean functions called PartitionedROBDDs. In this representation we divide the Boolean space into `k' partitions and represent a function ...
Amit Narayan, Jawahar Jain, Masahiro Fujita, Alber...
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
- Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the ...
Wojciech Maly, Hans T. Heineken, Jitendra Khare, P...
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
Designer's productivity has become the key-factor of the development of electronic systems. An increasing application of design data reuse is widely recognized as a promising...
We give a denotational framework (a "meta model") within which certain properties of models of computation can be understood and compared. It describes concurrent proces...