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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 8 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
ICCAD
2003
IEEE
161views Hardware» more  ICCAD 2003»
14 years 8 months ago
A General S-Domain Hierarchical Network Reduction Algorithm
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
Sheldon X.-D. Tan
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 8 months ago
Fredkin/Toffoli Templates for Reversible Logic Synthesis
Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate...
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
ICCAD
2003
IEEE
166views Hardware» more  ICCAD 2003»
14 years 8 months ago
Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems
Ambient Intelligent Systems provide an unexplored hardware platform for executing distributed applications under strict energy constraints. These systems must respond quickly to c...
Diana Marculescu, Nicholas H. Zamora, Phillip Stan...
ICCAD
2003
IEEE
100views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Theory of Non-Deterministic Networks
Both non-determinism and multi-level networks compactly characterize the flexibility allowed in implementing a circuit. A theory for representing and manipulating non-deterministi...
Alan Mishchenko, Robert K. Brayton
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 8 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 8 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
ICCAD
2003
IEEE
122views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Framework for Designing Reusable Analog Circuits
Dean Liu, Stefanos Sidiropoulos, Mark Horowitz
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
14 years 8 months ago
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning
Transmitting compressed data can reduce inter-processor communication traffic and create new opportunities for DVS (dynamic voltage scaling) in distributed embedded systems. Howe...
Jinfeng Liu, Pai H. Chou
ICCAD
2003
IEEE
219views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Min-Cost Flow Based Detailed Router for FPGAs
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
Seokjin Lee, Yongseok Cheon, Martin D. F. Wong