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ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 8 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 8 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Rece...
Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 8 months ago
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus, multiple compatible bus transactions can be performed simultaneously with only a...
Ruibing Lu, Cheng-Kok Koh
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 8 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
ICCAD
2003
IEEE
131views Hardware» more  ICCAD 2003»
14 years 8 months ago
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Leakage energy will be the major energy consumer in future deep sub-micron designs. Especially the memory sub-system of future SOCs will be negatively affected by this trend. In o...
Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel
ICCAD
2003
IEEE
170views Hardware» more  ICCAD 2003»
14 years 8 months ago
Evaluation of Placement Techniques for DNA Probe Array Layout
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis and ...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
ICCAD
2003
IEEE
134views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers
: Adaptive transceivers can significantly reduce the energy consumption of a mobile, battery-powered node by capturing realtime changes in the communication channel. This paper pro...
Ali Iranli, Hanif Fatemi, Massoud Pedram
ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
14 years 8 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ICCAD
2003
IEEE
158views Hardware» more  ICCAD 2003»
14 years 8 months ago
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages
Dynamic voltage scaling (DVS) is arguably the most effective energy reduction technique. The multiple-voltage DVS systems, which can operate only at pre-determined discrete voltag...
Shaoxiong Hua, Gang Qu