The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Symbolic image computation is the most fundamental computation in BDD-based sequential system optimization and formal verification. In this paper, we explore the use of over-appr...
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Efficient iterative time preconditioners for Krylovbased harmonic balance circuit simulators are proposed. Some numerical experiments assess their performance relative to the well...
Abstract: In this paper, we present an interprocessor communication-aware task scheduling algorithm applicable to a multiprocessor system executing an application with dependent ta...
This paper presents a generalized semi-analytic method for computing oscillator phase noise spectra, including the details very close to the oscillation frequency. The starting po...
Piet Vanassche, Georges G. E. Gielen, Willy M. C. ...
A fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-todigital converters (ADCs) in the presence of circuit nonidealities ...
Energy consumption is an important performance parameter for portable and wireless embedded systems. However, energy consumption must be carefully balanced with real-time responsi...
Emerging VLSI technologies and platforms are giving rise to systems with inherently high potential for runtime failure. Such failures range from intermittent electrical and mechan...