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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 8 months ago
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
Ansgar Stammermann, Domenik Helms, Milan Schulte, ...
ICCAD
2003
IEEE
98views Hardware» more  ICCAD 2003»
14 years 8 months ago
Achieving Design Closure Through Delay Relaxation Parameter
Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of ...
Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Cho...
ICCAD
2003
IEEE
131views Hardware» more  ICCAD 2003»
14 years 8 months ago
A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures
Detailed electromagnetic analysis of three-dimensional structures in multilayered dielectric media is critical for automatic generation of equivalent circuit models for the interc...
Ben Song, Zhenhai Zhu, John D. Rockway, Jacob Whit...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 8 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 8 months ago
Branch Merge Reduction of RLCM Networks
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
Bernard N. Sheehan
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 8 months ago
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
Navaratnasothie Selvakkumaran, George Karypis
ICCAD
2003
IEEE
119views Hardware» more  ICCAD 2003»
14 years 8 months ago
Dynamic Platform Management for Configurable Platform-Based System-on-Chips
Krishna Sekar, Kanishka Lahiri, Sujit Dey
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
14 years 8 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
14 years 8 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim
ICCAD
2003
IEEE
204views Hardware» more  ICCAD 2003»
14 years 8 months ago
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation
Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators ...
Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik ...