This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
Ansgar Stammermann, Domenik Helms, Milan Schulte, ...
Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of ...
Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Cho...
Detailed electromagnetic analysis of three-dimensional structures in multilayered dielectric media is critical for automatic generation of equivalent circuit models for the interc...
Ben Song, Zhenhai Zhu, John D. Rockway, Jacob Whit...
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators ...