New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
In this paper, we present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to re-place cells in order to avoid congested re...
Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, ...
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performanc...
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawren...
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
We extend the APlace wirelength-driven standard-cell analytic placement framework of [21] to address timing-driven and mixedsize (“boulders and dust”) placement. Compared with...