— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
In this paper we describe several novel sparsification techniques used in a Fast Stochastic Integral Equation Solver to compute the mean value and the variance of capacitance of ...
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, ...
High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is prop...
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wan...
State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However...
Process variations in nanometer technologies are becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and withindie va...
Abstract — This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. S...