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ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
14 years 8 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
ICCAD
2005
IEEE
96views Hardware» more  ICCAD 2005»
14 years 8 months ago
A more reliable reduction algorithm for behavioral model extraction
— In this paper we are concerned with developing more reliable model reduction algorithms. We have focused on less common, but real, examples that fail to be effectively reduced ...
Dmitry Vasilyev, Jacob K. White
ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
14 years 8 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 8 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
14 years 8 months ago
Performance analysis of carbon nanotube interconnects for VLSI applications
The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this ...
Navin Srivastava, Kaustav Banerjee
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 8 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
ICCAD
2005
IEEE
87views Hardware» more  ICCAD 2005»
14 years 8 months ago
Statistical technology mapping for parametric yield
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
ICCAD
2005
IEEE
160views Hardware» more  ICCAD 2005»
14 years 8 months ago
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
— This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapathoriented designs that implement polynomial computations over fixed-s...
Namrata Shekhar, Priyank Kalla, Florian Enescu, Si...
ICCAD
2005
IEEE
79views Hardware» more  ICCAD 2005»
14 years 8 months ago
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
Saumil Shah, Ashish Srivastava, Dushyant Sharma, D...