DATE
2005
IEEE
14 years 5 months ago
2005
IEEE
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
APCSAC
2005
IEEE
14 years 5 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
IEEECIT
2007
IEEE
14 years 5 months ago
2007
IEEE
Instruction window is a key component which extracts Instruction Level Parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor pe...
CGO
2007
IEEE
14 years 5 months ago
2007
IEEE
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
ICCD
2002
IEEE
14 years 8 months ago
2002
IEEE
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
VLSID
2004
IEEE
14 years 12 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...