— We report on a system designed for the magnetic control of nanoparticles and nanorods. This is accomplished by arrays of current-carrying wires (electromagnets) and the associa...
Edward Choi, Zhiyong Gu, D. Gracias, Andreas G. An...
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
— All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA in...
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
—A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate systemlevel integration, the new design can be developed in hardware des...
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
— This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application, and te...
— We consider the design of the MAC layer for low power, low data-rate, impulse-radio ultra-wide band (IRUWB) networks. In such networks, the primary concern is energy consumptio...
Ruben Merz, Alaeddine El Fawal, Jean-Yves Le Boude...
Abstract— Providing Quality-of-Service (QoS) in networks-onchip (NoCs) will be an important consideration for the complex multiprocessor chips of the future. In this paper, we di...