The purpose of this work is to explore how device operation parameters such as switching speed and power dissipation scale with voltage and temperature. We simulated a CMOS ring o...
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while op...
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Abstract - This paper studies design considerations for lowpower ultra wideband (UWB) receiver architectures. First, three different architectures for the impulse-radio UWB transce...
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...