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ISQED
2005
IEEE
119views Hardware» more  ISQED 2005»
14 years 5 months ago
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fa...
Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, ...
ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
14 years 5 months ago
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
— Multiple power supply voltages are often used in modern high performance ICs such as microprocessors to decrease power consumption without affecting circuit speed. The system o...
Mikhail Popovich, Eby G. Friedman
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
14 years 5 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
ISQED
2005
IEEE
90views Hardware» more  ISQED 2005»
14 years 5 months ago
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is ...
Oleg Semenov, H. Sarbishaei, Manoj Sachdev
ISQED
2005
IEEE
133views Hardware» more  ISQED 2005»
14 years 5 months ago
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao ...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
14 years 5 months ago
A More Effective CEFF
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
Sani R. Nassif, Zhuo Li
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 5 months ago
Welcome Notes
ISQED
2005
IEEE
64views Hardware» more  ISQED 2005»
14 years 5 months ago
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET
Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively use...
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaush...
ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
14 years 5 months ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
14 years 5 months ago
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourgu...