We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Modern network intrusion detection systems need to perform regular expression matching at line rate in order to detect the occurrence of critical patterns in packet payloads. Whil...
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
Memory bandwidth is frequently a limiting factor in the design of high-speed switches and routers. In this paper, we introduce a buffering scheme called ping-pong buffering, that ...
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
— Motion-compensated temporal filtering (MCTF) is an open-loop prediction scheme, so the frame-level data reuse for MCTF is possible. In this paper, we propose two general frame...
Depth traffic occupies a major portion of 3D graphics memory bandwidth. In order to reduce depth reading, we propose employing a low-resolution depth buffer, namely CoarseZ buffer...
Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua...
This paper proposes an efficient reference frame storage scheme for HDTV VLSI decoder to reduce external memory bandwidth requirement. The proposed scheme consists of the pixel du...