DATE
2000
IEEE
14 years 7 hour ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
ASPDAC
2009
ACM
14 years 8 days ago
2009
ACM
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
DATE
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper focuses on checking safety properties for sequential circuits specified on the RT-level. We study how different state encodings can be used to create a gate-level repr...
DSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
MTV
2007
IEEE
14 years 1 months ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
ICSE
2007
IEEE-ACM
14 years 7 months ago
2007
IEEE-ACM
The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for m...