This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register f...
Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, ...
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
ion for Asynchronous Design Verification Hao Zheng, Member, IEEE, Jared Ahrens, Tian Xia, Member, IEEE This paper presents a compositional method with preserving abstraction for sc...
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
Abstract--This paper presents a multiparameter momentmatching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi proc...
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...