VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
Functional decomposition is a process of splitting a complex circuit into smaller sub-circuits. This paper deals with the problem of determining the set of best free and bound var...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface ...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
15 years 25 days ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
VLSID
2003
IEEE
15 years 25 days ago
2003
IEEE
A formal synthesis method for complex real-time embedded software is proposed in this work. Compared to previous work, our method not only synthesizes embedded software with compl...