Sciweavers

34 search results - page 6 / 7
» A Methodology Based on Formal Methods for Predicting the Imp...
Sort
View
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 1 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
14 years 19 days ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
BMCBI
2007
147views more  BMCBI 2007»
13 years 7 months ago
Modeling biochemical transformation processes and information processing with Narrator
Background: Software tools that model and simulate the dynamics of biological processes and systems are becoming increasingly important. Some of these tools offer sophisticated gr...
Johannes J. Mandel, Hendrik Fuß, Niall M. Pa...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 8 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...