45 search results - page 6 / 9 » A New System Design Methodology for Wire Pipelined SoC |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
DATE
2003
IEEE
14 years 20 days ago
2003
IEEE
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...