522 search results - page 20 / 105 » A Note on Designing Logical Circuits Using SAT |
PATMOS
2004
Springer
14 years 20 days ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
CSREAESA
2004
13 years 8 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
GLVLSI
2003
IEEE
14 years 19 days ago
2003
IEEE
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...