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» A Small Test Generator for Large Designs
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VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
14 years 8 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
14 years 1 months ago
Functional test generation using property decompositions for validation of pipelined processors
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
Heon-Mo Koo, Prabhat Mishra
AIPS
2000
13 years 9 months ago
Plan Generation for GUI Testing
Graphical user interfaces (GUIs) have become nearly ubiquitous as a means of interacting with software systems. GUIs are typically highly complex pieces of software, and testing t...
Atif M. Memon, Martha E. Pollack, Mary Lou Soffa
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 4 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
TC
1998
13 years 7 months ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...