264 search results - page 41 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
ISCA
1997
IEEE
14 years 5 days ago
1997
IEEE
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardwa...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
SIGMETRICS
1997
ACM
14 years 24 days ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
TVLSI
2010
13 years 3 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...