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» A cell-based power estimation in CMOS combinational circuits
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TCAD
1998
127views more  TCAD 1998»
13 years 7 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
ISLPED
1996
ACM
89views Hardware» more  ISLPED 1996»
13 years 11 months ago
A novel methodology for transistor-level power estimation
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
14 years 1 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ARVLSI
2001
IEEE
258views VLSI» more  ARVLSI 2001»
13 years 11 months ago
Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits
We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFET's in their subthreshold region as well as c...
Vincent F. Koosh, Rodney M. Goodman
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong