34 search results - page 3 / 7 » A complete design for power methodology and flow for large A... |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
VLSID
2008
IEEE
14 years 1 months ago
2008
IEEE
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Curre...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...