179 search results - page 11 / 36 » A new test pattern generation method for delay fault testing |
128
Voted
ICCAD
2002
IEEE
16 years 14 days ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
138
Voted
ICES
2000
Springer
15 years 7 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
121
Voted
ICCAD
2000
IEEE
15 years 8 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
117
Voted
VTS
2003
IEEE
15 years 8 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
120
Voted
VLSID
1996
IEEE
15 years 7 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...